1. Field of the Invention
The present disclosure relates to a thin film transistor (TFT) substrate having a metal oxide semiconductor for flat panel displays and a method for manufacturing the same. Particularly, the present disclosure relates to a thin film transistor substrate and a manufacturing method the same for the flat panel display in which an oxide semiconductor material is formed after forming the source-drain electrode so that the channel area can be precisely defined.
2. Discussion of the Related Art
Nowadays, as the information society is developed, the requirements of displays for representing information are increasing. Accordingly, the various flat panel displays (FPDs) are developed for overcoming many drawbacks of the cathode ray tube (CRT) such as heavy weight and bulk volume. The flat panel display devices include the liquid crystal display device (LCD), the field emission display (FED), the plasma display panel (PDP), the organic light emitting display device (OLED) and the electrophoresis display device (ED).
The display panel of a flat panel display may include a thin film transistor substrate having a thin film transistor allocated in each pixel region arrayed in a matrix manner. For example, the liquid crystal display device represents video data by controlling the light transitivity of the liquid crystal layer using the electric fields. According to the direction of the electric field, the LCD can be classified in the two major types; one is vertical electric field type and the other is the horizontal electric field type.
For the vertical electric field type LCD, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are facing with each other for forming an electric field of which direction is perpendicular to the substrate face. A twisted nematic (TN) liquid crystal layer disposed between the upper substrate and the lower substrate is driven by the vertical electric field. The vertical electric field type LCD has merit of higher aperture ratio, while it has demerit of narrower view angle about 90 degree.
For the horizontal electric field type LCD, a common electrode and a pixel electrode are formed on the same substrate in parallel. A liquid crystal layer disposed between an upper substrate and a lower substrate is driven in In-Plane-Switching (IPS) mode by an electric field parallel to the substrate face. The horizontal electric field type LCD has a merit of wider view angle over 160 degrees and faster response speed than the vertical electric field type LCD. However, the horizontal electric field type LCD may have demerits such as low aperture ratio and transitivity ratio of the back light.
In the IPS mode LCD, for example, in order to form the in-plane electric field, the gap between the common electrode and the pixel electrode may be larger than the gap (or “Cell Gap”) between the upper substrate and the lower substrate, and in order to get enough strength of the electric field, the common electrode and the pixel electrode may have a strip pattern having certain width. Between the pixel electrode and the common electrode of the IPS mode LCD, the electric field horizontal with the substrate is formed. However, just over the pixel electrode and the common electrode, there is no electric field. That is, the liquid crystal molecules disposed just over the pixel electrodes and the common electrodes are not driven but maintain the initial conditions (the initial alignment direction). As the liquid crystal molecules in the initial condition cannot control the light transitivity properly, the aperture ratio and the luminescence may be degraded.
For resolving these demerits of the IPS mode LCD, the fringe field switching (FFS) type LCD driven by the fringe electric field has been proposed. The FFS type LCD comprises the common electrode and the pixel electrode with the insulating layer there-between, and the gap between the pixel electrode and the common electrode is set narrower than the gap between the upper substrate and the lower substrate. So that, a fringe electric field having a parabola shape is formed in the space between the common electrode and the pixel electrode as well over these electrodes. Therefore, most of all liquid crystal molecules disposed between the upper substrate and the lower substrate can be driven by this fringe field. As a result, it is possible to enhance the aperture ratio and the front luminescence.
For the fringe field type liquid crystal display, the common electrode and the pixel electrode are disposed closely each other or in an overlapped manner, so that a storage is formed between the common electrode and the pixel electrode. Therefore, the fringe field type liquid crystal display has a merit in that there is no extra space for forming the storage in the pixel region. However, when a large area display is formed in a fringe field type, the pixel region would be getting larger and the storage would be getting larger and larger. In that case, the thin film transistor should have also larger size for driving/charging the enlarged storage in a short time period.
To address this problem, the thin film transistor having a metal oxide semiconductor material is applied because it has the high current control characteristics without enlarging the size of the thin film transistor. FIG. 1 is a plane view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display according to the related art. FIG. 2 is a cross-sectional view illustrating the structure of the thin film transistor substrate of FIG. 1 by cutting along the line I-I′ according to the related art.
The thin film transistor substrate having a metal oxide semiconductor layer shown in FIGS. 1 and 2 includes a gate line GL and a data line DL crossing each other with a gate insulating layer GI therebetween on a lower substrate SUB, and a thin film transistor T formed at each crossing portion. By the crossing structure of the gate line GL and the data line DL, a pixel region is defined.
The thin film transistor T includes a gate electrode G branched (or ‘extruded’) from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S and connecting to the pixel electrode PXL, and a semiconductor layer A overlapping with the gate electrode G on the gate insulating layer GI for forming a channel between the source electrode S and the drain electrode D.
The semiconductor layer A made of the oxide semiconductor material has a merit for a large area thin film transistor substrate having a large charging capacitance, thanks to the high electron mobility of the oxide semiconductor layer. However, the thin film transistor having the oxide semiconductor material would have an etch stopper ES for protecting the upper surface of the semiconductor layer from the etching material for ensuring the stability and the characteristics of the thin film transistor. In more detail, it is proper to have an etch stopper ES for protecting the semiconductor layer A from the etchant used for forming the source electrode S and the drain electrode D there-between.
In the pixel region, a pixel electrode PXL and a common electrode COM are formed with the second passivation layer PA2 there-between, to form a fringe electric field. The common electrode COM is connected to the common line CL disposed in parallel with the gate line GL. The common electrode COM is supplied with a reference voltage (or “common voltage”) via the common line CL.
The common electrode COM and the pixel electrode PXL can have various shapes and positions according to the design purpose and environment. While the common electrode COM is supplied with a reference voltage having constant value, the pixel electrode PXL is supplied with a data voltage varying timely according to the video data. Therefore, between the data line DL and the pixel electrode PXL, a parasitic capacitance may be formed. Due to the parasitic capacitance, the video quality of the display may be degraded. Therefore, it is preferable to form the common electrode COM at first and then the pixel electrode PXL is formed at the topmost layer.
In other words, on the first passivation layer PA1 covering the data line DL and the thin film transistor T, a planarization layer PAC formed by thickly depositing an organic material having a low permittivity. Then, the common electrode COM is formed. And then, after depositing the second passivation layer PA2 to cover the common electrode COM, the pixel electrode PXL overlapping with the common electrode is formed on the second passivation layer PA2. In this structure, the pixel electrode PXL is far from the data line DL by the first passivation layer PA1, the planarization layer PAC and the second passivation layer PA2, so that it is possible to reduce the parasitic capacitance between the data line DL and the pixel electrode PXL.
The common electrode COM is formed to a rectangular shape corresponding to the pixel region. The pixel electrode PXL is formed to have a plurality of segments. Especially, the pixel electrode PXL is vertically overlapped with the common electrode COM with the second passivation layer PA2 there-between. Between the pixel electrode PXL and the common electrode COM, the fringe electric field is formed. By this fringe electric field, the liquid crystal molecules arrayed in plane direction between the thin film transistor substrate and the color filter substrate may be rotated according to the dielectric anisotropy of the liquid crystal molecules. According to the rotation degree of the liquid crystal molecules, the light transmittance ratio of the pixel region may be changed so as to represent desired gray scale.
In addition, for using a large current driving method in the active matrix type organic light emitting diode display, the thin film transistor substrate including a method oxide semiconductor material is increasingly required. For the organic light emitting diode display, referring to FIG. 2, an anode electrode (not shown) instead of the common electrode COM is formed as to be connected to the drain electrode D on the planar layer PAC, and an organic light emitting diode may be completed on the anode electrode. The structure of the thin film transistor T, the driving element, is commonly used for various type of flat panel display.
Nowadays, the thin film transistor substrate including a plurality of thin film transistor having the metal oxide semiconductor is mainly used in the flat panel display. As mentioned above, as the metal oxide semiconductor material is very weak against the developers, etchants and/or strip solutions used for the photo-lithography process, the semiconductor layer would be preferably protected by an etch stopper. Due to this structure, there may be various problems.
Hereinafter, one of the important problems caused in the thin film transistor substrate having the oxide semiconductor according to the related art will be explained. FIG. 3 is an enlarged cross-sectional view of circled portion {circle around (1)} in FIG. 2 for illustrating the structure of the thin film transistor having the oxide semiconductor material according to the related art.
On the gate insulating layer GI, depositing a metal oxide semiconductor material such as the Indium Gallium Zinc Oxide (IGZO) and patterning it in a mask process, a semiconductor layer A overlapped with the gate electrode G. Depositing an inorganic insulating material on the semiconductor layer A and patterning it with another mask process, an etch stopper ES covering some portions of the semiconductor layer A is formed. Then, depositing a source metal material and patterning it with yet another mask process, a source electrode S contacting the one exposed side of the semiconductor layer A from the etch stopper ES and a drain electrode D contacting the other exposed side of the semiconductor layer A from the etch stopper ES are formed.
During performing these 3 mask processes, the mask alignment clearance should be considered. That is, the etch stopper ES should have the length longer than the channel length plus at least the mask alignment clearance. Further, some portions of the source electrode S and the drain electrode D would be overlapped with the etch stopper ES. Here, we defined and/or called the overlapped portion between the source-drain electrodes S and D and the etch stopper ES as the overlapping area OVL.
In the thin film transistor having the metal oxide semiconductor material, this overlapping area OVL is one of main cause for degrading the characteristics of the thin film transistor. For example, in the organic light emitting diode display, the luminance would be controlled at the saturation area of the thin film transistor, when driving the organic light emitting diode of the organic light emitting diode display. In this case, if the saturation characteristics of the thin film transistor are not guaranteed, this may cause the luminance failure or distortion. In order to guarantee the saturation characteristics of the oxide thin film transistor, it is preferable for the size of the overlapping area OVL to be less than 1 μm (micrometer). However, it is very hard to make a large area thin film transistor substrate in which all thin film transistors have almost similar size of the overlapping area OVL.
Therefore, for developing, designing and mass producing the thin film transistor substrate having the oxide semiconductor material, it is required to ensure the technology in which the overlapping area would be minimized and/or eliminated, and all thin film transistors have the similar channel length.